Chemical mechanical polishing (CMP) is presently used to planarize a variety of materials used in semiconductor integrated circuit (IC) devices. For example, CMP is used to polish dielectric layers such as silicon dioxide, and metal layers such as tungsten, aluminum, and copper. Regardless of the material being polished, similar polishing techniques are used. For instance, all CMP polishing systems typically include a polishing platen, on which is attached a polishing pad. As the platen and pad are being rotated, a slurry is dispensed on a semiconductor wafer while the semiconductor wafer is pressed against the rotating pad at some predetermined force. A combination of the chemical reaction between the slurry and the layer-being-polished and mechanical interaction/force between the abrasive particles within the slurry and the layer-being-polished causes portions of the wafer layer to be removed and results in a planarization of a top surface of the wafer.
Referring to prior art FIG. 1, a low density structure 502, which will generally be an isolated electrical contact, is shown following a prior art metal polishing step. The feature 502 is an isolated feature in that there is no other other inlaid features of its type in close proximity thereto. Very isolated metallic regions which expose a small top surface area when compared to exposed top surface dielectric material are referred to as a low density feature areas. Because FIG. 1 shows a low density feature area, structure 502 is capable of being polished with the known CMP techniques discussed above without substantial dishing problems regardless of the type of polishing used. The polishing in FIG. 1 results in a substantially planar surface across the substrate 500. Note that there may be a slight difference in the height of the feature 502 relative to the surface of the substrate 500. This slight curvature or differnce in height of the surface of metal 502 after polishing is referred to as dishing. This dishing occurs because the prior art polishing slurry for polishing material 502 is usually chosen to be highly selective to the material 500, whereby the material 502 is etched at a fast rate while the oxide material 500 is etched at a much slower rate. This selectivity is chosen so that the process can endpoint on the layer 500 and/or can over-polish for a substantial period of time to improve process control and yield without substantial oxide damage.
However, the percentage of exposed metal area after the oxide 500 is exposed by polishing is very small. In other words, the exposed metal regions 502 are typically contacts in FIG. 1 and have very small footprints when viewed from a top perspective (the contacts has a top footprint surface area of less than 1 micron). Therefore, with the structure of FIG. 1 there is no substantial dishing problem regardless of the use of high selectivity polishing or low selectivity polishing and regardless of over-polish times due to the fact that the metal contacts have a very small footprint. Accordingly, tungsten plug contact polishing and like low density polishing have not presented dishing problems whereby focus on selectivity is needed, and therfore, the CMP art has generally ignored selectivity as it pertained to polishing in this context.
Referring to the prior art FIG. 2, features 506, which may also be of the same type as feature 502, are shown in a high density configuration. In the high density configuration, as illustrated in prior art FIG. 2, the polishing process has the effect of creating erosion or substantial dishing of the high density region. Specifically, as polishing progresses to expose the underlying oxide layers by removing top portions of the metal layer 506, the interaction between the polishing pad and the surrounding silicon dioxide is such that the polishing forces encourage an erosion or breaking away the oxide corners adjacent metal regions. This erosion effect, as illustrated in FIG. 2, further encourages the creation and continuation of a dishing effect whereby oxide and metal in dense metal areas are eroded whereby one or more dishing regions result as illustrated in FIG. 2. As a result, the topography of the wafer between high density regions and low density regions is very different resulting in a non-planar surface. In addition, many contacts 506, as illustrated in FIG. 2, may be adversely thinned as compared to other contacts on the same itnegrated circuit (IC). Differences in planarity across a wafer and selective erosion of via metal in dense areas are disadvantageous in the IC industry. Therefore, for high selective polishing, the polishing of both low density and high density regions on the same wafer is problematic.
FIG. 3 illustrates a further ramification of the disadvantageous dishing effect as is known in the prior art. Specifically, when a feature 504 having a large width (generally greater than 20 microns) is formed and polished, a dishing effect occurs wherein the feature 504 will have a lesser thickness near the center of the feature 504 as opposed to the edge of the feature 504 which is adjacent the surrounding oxide sidewall. Therefore, polishing metal layers lying within both larger dimension openings and small openings on an IC is problematic due to the larger dimension dishing and erosion that occurs with high selectivity CMP processing. Since dual inlaid interconnects involve both high density and low density regions and large disparity between opening dimensions, high selectivity polishing is not optimal for modern integrated circuit design given the disproportionate dishing phenomena illustrated in FIGS. 1-3.
Prior solutions to the dishing and erosion problems are numerous. One prior art solution has dealt with optimizing the polishing process for a specific device structure. For example, if a given layer is known to contain closely space interconnect lines, the process would be optimized to this dense structure type. Another solution has been to limit the amount of over-polish used with selective polishing processes. Yet another solution has been to add intra die dummy structures to make a device having a more uniform density, allowing for the use of an optimized polishing process. All of these solutions are complex and not without added cost.
In summary, in the prior art where Tungsten plugs have been polished with CMP, the affects of intra-die topographies do not come into play due to the small dimension of the resulting contact plugs. Regardless of the selectivity of the polishing process, the resulting topography will be substantially planar following the deposition of a metal layer. Therefore, the polish process which removes the excess tungsten from the surface is not a critical function of selectivity. Historically, this process would occur with an alumina abrasive and an oxidizing agent without selectivity being a concern. The use of the alumina agent has been used primarily because of the hardness of alumina and the increased polishing rate which can be achieved.
For interconnect layers of larger density than tungsten-plugged contacts, the use of high selectivity CMP processes has been used in order to define the planar surface to be substantially even with the surrounding oxides of the interconnect features. However, as previously discussed, the high selectivity prior art methods described previously cause the dishing, and erosion, as illustrated previously with references to FIG. 2 and FIG. 3.
Therefore, it would be beneficial to identify a low-selectivity polishing method which allows for uniform polish processing on interconnect levels where various feature sizes, densities, and structures are present while reducing the dishing and erosion problems discussed hereinabove.